Recent, developments have included various techniques for increasing the density of integration of the semiconductor memory device. In a dynamic random access memory (DRAM), various cell structures are proposed for miniaturizing the size of the device.
In view of miniaturizing the size of the device for increasing the density of integration, it is preferable that memory cell has one transistor and one capacitor. In the memory cell having one transistor and one capacitor, electric charges are stored at storage node of the capacitor connected to the transistor (switching transistor).
If the size of the memory cell is miniaturized by increasing the density of integration, the size of the capacitor is small and the number of the electric charges to be stored at the storage node are decreased. However, the storage node should have a predetermined surface area so that the capacitance for transmitting a desired signal without error can be provided. To miniature the size of memory cell, the storage node of the capacitor is to have the large surface area relatively in a limited area.
Among the proposed memory cell structures, a stack capacitor has an advantage that the high density of integration is profitable and the effect of soft error is reduced. Also, the memory cell having the stack capacitor is suitable to a mass production and the processes for fabricating thereof is easy.
The structure of stack capacitor for increasing the capacitance of capacitor is disclosed in, e.g., U.S. Pat. No. 4,742,018.
FIG. 1(a) to 1(g) are sectional views showing the production steps of the conventional art.
In FIG. 1(a), there is a p-type silicon substrate 1 on which a switching transistor is formed. The transistor includes n-type semiconductor regions to be used as the source and drain regions and a gate 2 and a gate insulator 3. After a first oxide film 6 is deposited on the whole surface, selective etching is performed to form contact holes so that the source and drain regions 5 are exposed.
A first conductive layer 8 is deposited thereon so that the first conductive layer 8 is connected to the source and drain region 5 through the contact hole, as shown in FIG. 2(b). And the first conductive layer 8 is patterned by photholithography technique using a capacitor storage node pattern.
A second oxide film 9 is deposited thereon and is selectively etched away so that a contact hole is formed to expose a part of the first conductive layer 8, as shown in FIG. 1(c).
A second conductive layer 10 is deposited thereon to connect to the first conductive layer 8 electrically through the contact hole formed at the second oxide layer 9, as shown in FIG. 1(d).
And the second conductive layer 10 is patterned by using the capacitor storage node pattern.
The second oxide layer 9 is removed by wet etching to form a capacitor storage node 11 including the first conductive layer 8 and the second conductive layer 10, as shown in FIG. 1(e).
A capacitor dielectric film 12 is formed on the exposed surface of the storage node 11 as shown in FIG. 1(f). A conductive material is deposited on the capacitor dielectric film 12 and is patterned to form a capacitor plate electrode, as shown in FIG. 1(g).
However, for fabricating the capacitor of multi-layer to increase furthermore the capacitance of the capacitor, it is a problem that the processes are added and the soft error is placed.